1. Field of the Invention
The present disclosure relates to circuitry and a method for pixel processing, and in particular to circuitry and a method for performing a function based on a plurality of pixel values read from a pixel array.
2. Description of the Related Art
The processing of pixel values of a captured image generally involves reading the pixel values from a pixel array in an analog form, converting these analog pixel values into digital pixel values, storing the digital pixel values in a memory, and then using an image processor, such as an FPGA (Field Programmable Gate Array), to process the digital values.
A drawback of this type of digital pixel processing is that it is relatively demanding in terms of processing power and resources, and/or it is time consuming.
It has been proposed to perform at least some pixel processing during the digital conversion of the analog pixel values. In particular, the paper entitled “An Architecture for Low-Power Real Time Image an Analysis Using 3D Silicon Technology”, Lisa McIlarth and Paul Zavracky, describes a system based on Sigma Delta analog to digital converters (Sigma Delta ADCs).
FIG. 1 reproduces FIG. 6 of the McIlarth paper. The outputs of an array of photo sensors are provided in parallel to Sigma Delta ADCs, one of which is provided per pixel. The outputs from the Sigma Delta ADCs are then provided to an 8-bit accumulator array, which converts the pulses produced by the Sigma Delta converters into digital values, which are stored in a RAM (Random Access Memory).
A Sigma Delta ADC generates a stream of pulses, the number of pulses being proportional to the sampled analog value. The 8-bit accumulators count the number of pulses in order to generate a digital value proportional to the analog pixel value. McIlarth describes some relatively basic pixel operations that can be performed when converting the Sigma Delta signals into digital values. For example, in order to determine the difference between two pixels, the corresponding Sigma Delta signals are coupled respectively to the positive and negative inputs of an up/down counter.
There are a number of drawbacks with such a solution based on Sigma Delta ADCs. In particular, the need to provide a Sigma Delta converter per pixel makes the architecture relatively consuming in terms of silicon area. Furthermore, while McIlarth suggests that the outputs of several Sigma Delta ADCs could be multiplexed to each accumulator, such an implementation would be rather limited, given that all of the Sigma Delta signals are generated over the same period of time.
Furthermore, in order to perform more that one operation on each pixel value, it would be necessary to couple the output of each Sigma Delta ADC to more than one accumulator. The repeated charging and discharging of these outputs would lead to high energy consumption.